sse

sse

Intel vector instruction to zero-extend 8 4-bit values packed in a 32-bit int to a __m256i?

Check all bytes of a __m128i for a match of a single byte using SSE/AVX/AVX2

Multiply bytes to produce 16-bits, without shifting

Substitute a byte with another one

Character to bits with SIMD (and substrings)

Do all CPUs which support AVX2 also support SSE4.2 and AVX?

1-to-4 broadcast and 4-to-1 reduce in AVX-512

How to copy the lower part of the lanes of a XMM register with libsimdpp

How to compile program with SIMD instruction '_mm_exp_ps()' on OS X [duplicate]

SSE/AVX: Choose from two __m256 float vectors based on per-element min and max absolute value

Shift right every DW in a __m128i by a different amount

What is the difference between loadu_ps and set_ps when using unformatted data?

Is there an SIMD instruction to achieve batch array memory index mapping?

SSE - Non-Existant haddsub intrinsic?

AVX2: How to move a single element from vector to vector

AVX2: U8 absolute difference

atan2 approximation with 11bits in mantissa on x86(with SSE2) and ARM(with vfpv4 NEON)

sse/avx equivalent for neon vuzp

Intel modular arithmetic using AVX or SSE

Do the Airmont cores on Knight's Landing Xeon Phi's support SIMD instructions?

How does _mm_mul_ps() add two __m128?

avx slower then sse multimedia extensions

Is there a SSE2 equivalent for _mm_insert_epi32?

Converting gausian function into SSE

Shuffle 16 bit vectors SSE

Bitwise xor of two 256-bit integers

AVX instructions generated when -xSSE4.1 specified

SSE instruction to sum 32 bit integers to 64 bit

Can we use SSE intrinsics to write to a memory mapped PCI device memory

eigen vectorization with arrays

Fastest way to move higher or lower 64 bits in integer SSE register

Effective way to extract from SSE vector on AMD processors

determinant calculation with SIMD

What is the difference between non-packed and packed instruction in the context of SIMD-operations?

how to use SSE instruction in the x64 architecture in c++?

AVX equivalent for _mm_storeu_ps?

For XMM/YMM FP operation on Intel Haswell, can FMA be used in place of ADD?

can someone explain this SSE BigNum comparison?

practical BigNum AVX/SSE possible?

Altivec Programming Resource [closed]

Can multiple processes hide latency of SSE instructions?

implications of using _mm_shuffle_ps on integer vector

SSE: why, technically, is 16-aligned data faster to move?

can't find materials about SSE2, Altivec, VMX on apple developer

Calculating constants for CRC32 using PCLMULQDQ

Parallel programming using Haswell architecture [closed]

Can I move a float stored in a _m128 SSE register directly to a normal register?

Implict SSE/AVX loads/stores and the stack

_mm_srli_si128 equivalent on altivec

extremely slow program from using AVX instructions

Did the Streaming SIMD Extensions replace x87 instruction set?

SIMD math libraries for SSE and AVX

x264 library speed - Altivec vs SSE4 -

Relationship between SSE vectorization and Memory alignment

SSE performance vs normal code

How to sum __m256 horizontally?

False autovectorization in Intel C compiler (icc)

load 32 bits from memory into xmm register

Efficient way to create a bit mask from multiple numbers possibly using SSE/SSE2/SSE3/SSE4 instructions

Where can I find a reference for the AMD FMA 4 intrinsics?

page:1 of 2 next page main page

Categories

visual-studio-2010

react-datepicker

azure-resource-group

information-schema

react-styleguidist

jquery-select2-4

software-quality

objectinputstream

windows-phone-7

android-broadcast

jmeter-maven-plugin

bootstrap-native

elasticsearch-py

mpmovieplayercontroller

sql-server-ce-3.5

html5-validation

reactive-banana

db2-content-manager

sql-server-administration

Resources